Two-dimensional (2D) semiconductors are gaining considerable attention far beyond silicon electronics because of their ultrathin bodies and high carrier mobility (1, 2). Recently, the discovery of the excellent electronic performance of black phosphorus (BP) transistors has stimulated widespread research interest. Experiments have shown that the BP field-effect transistors (FETs) exhibit ambipolar behavior with on/off ratio up to 106 and mobility up to ~1000 cm2/V·s (3). Meanwhile, the direct bandgap of BP varies from 0.3 eV (bulk) to 2.0 eV (monolayer), making it suitable for applications in optoelectronics, especially in the infrared regime (4). Since 2014, many efforts have been made on the 2D BP films with regard to logic and optoelectronic applications (5, 6); high-performance BP devices under high electric field are still lacking. One issue is the formation of Schottky barriers at the interface between BP and metal contacts, resulting in relatively large contact resistance (Rc) that severely limits the device performance especially in short-channel regime (7, 8). Most previous works focus on high work function metal or chemical doping to enhance the hole injection and decrease the Rc (5, 9). However, typical contact resistance values resulting from these methods are still around 1 kilohm·μm, and the drive current of these devices is limited in the range of 0.2 to 0.7 mA/μm. As a result, effective doping approach for high-performance BP transistors is still lacking. In addition, it has been well known that the impurities and the dielectric environment play important roles in the electrical and optical properties of the sensitive BP materials (10). So far, most studies focus on BP devices with thick thermally oxidized SiO2 as back-gated dielectrics, which typically yield unsatisfactory electronic properties (3–5, 9). Therefore, the integration of high-quality dielectrics with BP is an important scientific and technological challenge. Another unique property of BP is its anisotropic properties due to the highly asymmetric effective mass, which enables the use of the lower effective carrier mass transport along the armchair direction for better performance transistors (4). Moreover, saturation velocity plays a substantial role in determining device performance especially in short-channel transistors, and hole saturation velocity in conventional semiconductors and 2D transition metal dichalcogenides is typically much lower than that of electrons. High hole saturation velocity in BP 2D semiconductors is vital for realizing high-performance optoelectronics and electronics (11). However, very few studies of saturation velocity in short-channel BP FETs have been reported to date despite the importance in fundamental and practical application.
In this work, we introduce an ultrathin high-k HfLaO as the back gate dielectric to increase the electrostatic doping and improve the interface quality. The equivalent oxide thickness of the HfLaO dielectric in this work is around 2.7 nm. The application of −4 V back gate (Vbg) voltage induces a much higher carrier density of 2.1 × 1013 cm−2 than those using the typical SiO2, owing to the combination of high-k property and excellent dielectric breakdown property. The high carrier density results in an increase of electrostatic doping of BP underneath the metal contact with a lower Schottky barrier, which facilitates the hole injections from the source metal into the channel that results in a reduced Rc. The minimal Rc of 0.7 kilohm·μm and the maximum drain current of 1.2 mA/μm for the 100-nm channel length BP device are obtained at room temperature. Furthermore, the drain current increases to around 1.6 mA/μm at 20 K when ballistic transport is effectively realized. In addition, we extract a saturation velocity of 1.5 × 107 cm/s at room temperature, which outperforms silicon and other layered 2D semiconductors and reaches the highest value for hole saturation velocity.
We mechanically exfoliated layered BP flakes from bulk crystal (smart elements) and then transferred them onto a p++ Si substrate covered with HfLaO dielectric layer. The dielectric constant of the HfLaO film is 26 (figs. S1 to S3). The schematic view of the dual-gated devices in this work is shown in Fig. 1A. The channel region is defined by electron beam lithography and followed by a 20-nm Ni/60-nm Au metal stack by electron beam evaporation as source and drain electrodes. The BP flakes were identified by a combination of optical microscopy and atomic force microscopy (AFM) with typical thickness around 12.5 nm, as shown in Fig. 1B. Raman spectra on the 12.5-nm-thick BP flake with the excitation laser polarized along three different directions are shown in the left panel of Fig. 1C. The three characteristic Raman modes, A1g, B2g, and A2g, can be observed, corresponding to the out-of-plane vibration along the z axis (~361 cm−1), in-plane vibration along the y axis (zigzag) (~438 cm−1), and armchair (~466 cm−1) directions along the x axis, respectively (4, 5). As shown in the A2g/A1g intensity ratio in 180° rotation of the sample in the right panel of Fig. 1C, it is clear that the intensity ratio reaches the maximum and minimum values when the laser polarization is parallel to the x (armchair) and y (zigzag) directions, respectively, consistent with the anisotropy of BP (4). Figure 1D shows a typical scanning electron microscopy (SEM) image of the fabricated BP transistors, with a channel length of 100 nm in this work. To achieve the best performance, we aligned the metal contact to the zigzag crystal direction of the BP flake to achieve the electronic transport in the channel along the armchair direction (4).
(A) Schematic of a back-gated BP on an HfLaO substrate with top Ni/Au source and drain electrodes. (B) BP flake with a measured thickness of 12.5 nm by AFM. Inset of (B), AFM image of the few-layer BP devices. Scale bar, 2 μm. (C) Polarization-resolved Raman spectrum of the BP flake. The left image shows three spectra obtained from an individual flake in different orientations. The right image shows the orientation-dependent A2g/A1g peak intensities. (D) Representative false-colored SEM image of the BP transistors. AC and ZZ stand for the armchair and zigzag directions, respectively. Scale bar, 1 μm. a.u., arbitrary units.
Figure 2A shows the well-behaved output characteristics of BP FETs with the 100-nm channel length at room temperature. A maximum drain current (Idmax) of 1.2 mA/μm is realized at Vd = −2.5 V and Vbg = −4 V, which is the highest on-current density reported for BP transistors at room temperature to date, to the best of our knowledge (12, 13). As shown in Fig. 2B, a record-high Idmax of 1.6 mA/μm is obtained at Vd = −2.5 V and Vbg = −5 V at 20 K, which is the highest current reported thus far for all 2D semiconductor materials (12, 13). The corresponding transfer characteristics for the same BP device are shown in fig. S4 (A and B). Contact resistance Rc is extracted using the transfer length method, and the result is shown in fig. S5A. In addition, the Schottky barrier height of metal-BP contacts shows a strong back gate dependence, and a very small contact resistance can be achieved at higher doping densities from the back gate voltage (fig. S5, A and B). The details of the carrier injection mechanism are shown in fig. S5 (C to E). The gate voltage of the minimum drain current (Vmin) for BP on the HfLaO dielectric substrate remains the same as the temperature decreases from 300 to 20 K, as shown in Fig. 2C, suggesting minimal interface trap charges between the BP flake and the HfLaO dielectric. This can be further confirmed by plotting the difference of threshold voltage during double sweeps at different temperatures, as shown in Fig. 2D, showing that the gate voltage hysteresis is independent of temperature. The weak temperature dependence of the Vmin and hysteresis indicates reduced interface trap densities and charge inhomogeneities (14, 15).
(A) Output characteristics of the BP device with a channel length of 100 nm at 300 K. (B) Output characteristics of the same device at 20 K. (C) Transfer characteristics of the 100-nm device for BP on HfLaO at different temperatures. (D) Hysteresis values of the 100-nm device for BP on HfLaO as a function of temperature.
We assume that the electric field and charge are uniform along the channel and ignore the drain-induced barrier-lowering effect. In this case, the carrier velocity